IIT Delhi researchers develop India’s first indigenous micro-GPU

Researchers at the Indian Institute of Technology Delhi have developed what the institute describes as India’s first working, demonstrable indigenously designed micro-Graphics Processing Unit (micro-GPU).

The project has been developed by researchers from IIT Delhi’s Department of Electrical Engineering and is aimed at enabling indigenous graphics and display-processing systems for embedded applications.

The project was led by MTech students Nammi Akash and M Ravi Teja under the guidance of professors Jayadeva and Kaushik Saha.

The researchers have demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL).

The design has been mapped onto a Spartan-7 Field Programmable Gate Array (FPGA) platform, allowing the researchers to demonstrate the working graphics-processing architecture.

IIT Delhi describes the hardware as a scalable and programmable graphics processor intellectual property that can potentially be implemented on Application-Specific Integrated Circuits (ASICs) or programmable hardware such as FPGAs.

Designed for embedded applications

The micro-GPU is intended for applications that require graphics and display processing but may not need the capabilities of larger, high-performance GPUs.

Potential applications identified by the researchers include industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats and educational e-book readers.

The institute said the technology could support affordable embedded visualisation systems.

Team plans 8–16-core architecture

The researchers are now exploring an 8–16-core vector-style graphics processor architecture, along with an optimised compiler and graphics software toolchain.

The team is also looking at a future proof-of-concept implementation using a 65 nm ASIC process node. IIT Delhi said the researchers believe mature semiconductor process nodes such as 65 nm could potentially support economically viable graphics silicon for embedded applications.

The project is currently at the research and development stage. The team plans to seek funding for ASIC development, system integration and eventual commercialisation of the technology.

IIT Delhi said the project demonstrates the potential for developing programmable graphics hardware within India and provides students with experience spanning arithmetic hardware, programmable architectures, compilers and embedded systems.

The researchers described the objective as developing a compact programmable graphics-processing architecture that can work on FPGA platforms and eventually be realised through ASIC technology.